1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to fabricating a transistor having a metal silicide formed in close proximity to the gate.
2. Description of the Related Art
Fabrication of silicon integrated circuits involves the creation of isolated device active regions within a single-crystal substrate. High-conductivity, thin-film structures fabricated over isolation and interlevel dielectric regions are used to connect these devices. Generally, metal-semiconductor contacts exhibit resistance to the flow of current across the contact due to differences between the work function of the semiconductor and the work function of the metal. It is thus necessary to modify the contact such that it exhibits a near-linear current-voltage relationship in both directions of current flow and such that it possesses negligible resistance when compared to the bulk resistance of the semiconductor.
One way to do this is to heavily dope the semiconductor substrate, which increases charge transport across the metal-semiconductor contact due to quantum-mechanical tunneling. Because contact resistance is inversely proportional to the surface concentration of the dopant, it would seem desirable to dope the substrate with as heavy a dopant concentration as is possible. The maximum doping concentration, however, is limited by the solid solubility of the dopant within the substrate at the temperature at which the dopant is introduced and by dopant clustering effects.
Further, as device dimensions have shrunk, it has become necessary to reduce the depth of the doped junction regions. This has limited the ability of the doped regions alone to reduce the resistance of the contact, because forming shallower junctions typically necessitates decreasing the dopant concentration. In addition, as the contact dimensions decrease, the contact resistance increases, as does the resistivity of the shallow junctions. Self-aligned silicide ("salicide") technology can be used to reduce these resistance values. According to the salicide technique, a metal is deposited across a MOSFET and reacted with exposed silicon areas of the source and drain, as well as exposed polysilicon areas on the gate, to form a silicide.
The area of the silicon-silicide interface is much larger than the area of a silicon-metal contact. In addition, the metal-silicide contact resistance is much lower than the metal-silicon resistance. As such, the salicide process allows a reduction in contact resistance. Formation of a metal silicide upon the contact areas is not, however, without some disadvantages. For example, in order to prevent shorting of the junctions to the gate conductor, insulating spacers must be formed adjacent the gate. The spacers prevent deposition of metal upon the sides of the polysilicon gate conductor. Because silicides typically do not form upon the spacers, the spacers also prevent "bridging" between silicide formed upon the junctions and silicide desirably formed upon the gate conductor upper surfaces ("polycide"). The spacers, however, separate the silicide from the channel region, such that current still must flow some distance from the contact through the higher-resistivity silicon substrate to reach the channel.
In addition, during silicide formation, a portion of the substrate is consumed. If the silicide is formed over a shallow junction, the formation process must be carefully monitored to ensure that the shallow junction is not totally consumed. As such, it would be desirable to fabricate a transistor having silicide formed over a shallow junction without the danger of consuming the junction region during processing. It would further be desirable to fabricate a transistor having metal silicides formed in close proximity to the gate to decrease the resistivity associated with the source-to-drain conductive pathway.